Chip Placement with Diffusion

Vint Lee, Chun Deng, Leena Elzeiny, Pieter Abbeel, and John Wawrzynek, Chip Placement with Diffusion, arXiv:2407.12282.

Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power consumption, area, and performance. Existing learning-based methods typically fall short because of their reliance on reinforcement learning, which is slow and limits the flexibility of the agent by casting placement as a sequential process. Instead, we use a powerful diffusion model to place all components simultaneously. To enable such models to train at scale, we propose a novel architecture for the denoising model, as well as an algorithm to generate large synthetic datasets for pre-training. We empirically show that our model can tackle the placement task, and achieve competitive performance on placement benchmarks compared to state-of-the-art methods.

Challenges of diffusion model:

Training a large and generalizable diffusion model, however, comes with its own challenges. First, the vast majority of circuit designs and netlists of interest are proprietary, severely limiting the quality and quantity of available training data. Secondly, many of these circuits are also large, containing hundreds of thousands of macros and cells. The denoising model used must therefore be computationally efficient and scalable, in addition to working well within the noise-prediction framework.